1. Field of the Invention
This invention relates to the manufacture of integrated circuits and more particularly to the manufacture of microcontrollers.
2. Description of the Relevant Art
A typical computer system includes a microprocessor secured within its own semiconductor device package and connected to several separately-packaged support circuits. The support circuits perform support functions such as communication functions and memory interface functions. A microcontroller is an integrated circuit which incorporates a microprocessor core along with one or more support circuits on the same monolithic semiconductor substrate (i.e., chip). Computer systems which employ microcontrollers may thus be formed using fewer semiconductor devices. Advantages of such systems include lower fabrication costs and higher reliabilities. Microcontrollers find applications in industrial and commercial products including control systems, computer terminals, hand-held communications devices (e.g., cellular telephones), photocopier machines, facsimile machines, and hard disk drives.
Asynchronous serial communication is the standard means of transmitting data over distances greater than about 25 feet. In serial data communication, each unit of data (e.g., an 8-bit byte representing a character) is transmitted one bit at a time over a transmission medium (e.g., a pair of wires, a coaxial cable, etc.). FIG. 1a is a diagram of a data "frame" used in asynchronous serial communication. The data frame includes multiple data bits 2 transmitted between a "start" bit 4 and one or more "stop" bits 6. Data bits 2 include n bits of a data unit, D.sub.0 through D.sub.n-1 where n is typically 7 or 8, and an optional parity bit 8 which may be added to facilitate error detection. Start bit 4 is always a 0 and signals the beginning of the frame. The one or more stop bits 6 are always a 1 and signal the end of the frame. Start bit 4 and the one or more stop bits 6 are used to synchronize a transmitter and a receiver during asynchronous serial communication. The transmitter and receiver must both use the same set of rules designating how many bits are transmitted per second (i.e., the baud rate), how many bits are included in a data unit, whether a parity bit is included, and how many stop bits are added after the data bits.
Due to the prevalence of serial data communication, many microcontrollers include one or more asynchronous serial ports (ASPS) which can transmit and/or receive data one bit at a time. Such microcontrollers typically employ interrupt signals to notify the microprocessor core that an ASP requires service. An ASP typically issues an interrupt request signal when a data unit has been received by the ASP and needs to be transferred from the ASP to an external memory unit, or when the ASP has finished transmitting a data unit and the next data unit to be transmitted must be transferred from the external memory unit to the ASP.
The microprocessor core executes instructions of software programs. Upon receiving an interrupt request signal from the ASP, the microprocessor core stops program execution, saves the contents of certain critical registers (i.e., saves its internal state), and begins executing instructions of an appropriate interrupt service routine (i.e., an interrupt handler) associated with the ASP. When execution of the interrupt service routine is completed, the microprocessor core restores the saved contents of the critical registers (i.e., restores the internal state) and resumes execution of the interrupted program at the point where the interruption occurred.
When interrupts are used to service an ASP, the microprocessor core must first save its internal state and execute a portion of the instructions of the interrupt service routine. The amount of time required to perform these actions places an upper bound on the number of bits the ASP may transmit or receive each second (i.e., the maximum operational baud rate of the ASP). In addition, the microprocessor core must interrupt program execution in order to service the ASP, negatively impacting the performance of the microprocessor core.
Direct memory access (DMA) is a well known technique which allows data transfers without involving the microprocessor core. In addition, many microcontrollers include a DMA unit which controls DMA data transfer operations. The microprocessor core simply initializes control registers within the DMA unit with transfer control information. The transfer control information typically includes the first address of the source of the block of data to be transferred (i.e., the source address), the first address of the destination of the block of data to be transferred (i.e., the destination address), and the number of bytes or words to be transferred (i.e., the byte/word count).
When a device needs to transfer data, the device generates a DMA request signal. The DMA unit responds to the DMA request signal by gaining control of the common bus interconnecting the involved devices and initiating the data transfer operation. The DMA unit generates address and control signals needed to read a byte or word of data from the source address and to write the data to the destination address. After each read/write operation, the source and destination addresses and the byte/word count are either incremented or decrement. This process is continued until the data transfer operation is complete. When the data transfer operation is complete, the DMA unit relinquishes control of the common bus.
9-bit serial protocols are increasingly being used to transfer data using asynchronous serial communication. FIG. 1b is a diagram of a data frame used by 9-bit serial protocols. The data frame includes multiple data bits 2 transmitted between a "start" bit 4 and one or more "stop" bits 6. Data bits 2 include 8 bits of a data unit, D.sub.0 through D.sub.7, and a ninth data bit D.sub.8, labeled 9 in FIG. 1b, in place of optional parity bit 8 (FIG. 1a). Ninth data bit 9 (bit D.sub.8) is set to 1 to indicate the beginning and/or end of a message spanning multiple data units (i.e., the beginning and/or end of a data packet). 9-bit serial protocols are commonly used to manage communications between multiple microcontrollers coupled to a common transmission medium. In this case, each data packet typically includes one or more "header" frames at the beginning of the data packet. Each data packet may also include one or more "trailer" frames at the end of the data packet. One of the header frames typically includes a unique device identification (ID) number assigned to the intended receiver. The trailer frames may include, for example, the last data units of the data packet or a cyclic redundancy check (CRC) value for error detection. Ninth data bit 9 is set to 1 in the header and trailer frames and is set to 0 in other data packet frames.
It would thus be desirable to have a microcontroller which is configurable to transfer data to and from one or more ASPs using DMA, and having hardware features which notify the microprocessor core when complete data packets transmitted using a 9-bit serial protocol are received. DMA data transfers increase the maximum baud rate of each ASP and improve the performance of the microprocessor core during ASP operation. When the microprocessor core is involved in the transfer of serial communication data, the microprocessor core is able to determine the beginning and end of data packets transmitted using a 9-bit serial protocol. The use of DMA to accomplish such data transfers does not allow for such a determination. When DMA is used to transfer serial communication data transmitted using a 9-bit serial protocol, additional hardware features are needed to notify the microprocessor core when complete data packets are received.